14. Coprocessor 0

14.21 ECC Register (26)

The R10000 processor implements a 10-bit read/write ECC register which is used to read and write the secondary cache data ECC or the primary cache data parity bits. (Tag ECC and parity are loaded to and stored from the TagLo register.) Unlike the R4400, the only CacheOps that use ECC register are Index Load Data and Index Store Data.

In the R4400, both the primary instruction and data caches are parity byte-protected.

In the R10000 processor, the following protection schemes are used:

The primary instruction cache is word-protected (where one word contains 36 bits), and one parity bit is used for each instruction word (IP in Figure 14-23).
The primary data cache is byte-protected, with four bits used for each 32-bit data word (DP in Figure 14-23).
Each quadword of the secondary cache data uses nine bits of ECC and one bit of parity (SP and ECC in Figure 14-23).

The primary instruction CacheOps load or store one instruction word at a time; therefore, one bit is used in the ECC register. The primary data CacheOps load or store four bytes at a time; therefore, four bits are used in the ECC register. The secondary CacheOps use ECC[9] as the parity bit and ECC[8:0] as the 9-bit ECC. For the Index Store Data CacheOps, the unused bits are ignored. For Index Load Data CacheOps, the unused a bits are with zeroes.

Figure 14-23 shows the format of the ECC register; Table 14-23 describes the register fields.

Figure 14-23 ECC Register Format

Table 14-23 ECC Register Fields

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